Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style
| Autor: | Fu-Wei Chen, Yi-Yu Liu |
|---|---|
| Rok vydání: | 2010 |
| Předmět: |
Interconnection
Engineering business.industry Integrated circuit design Power factor Integrated circuit Routing architecture Computer Graphics and Computer-Aided Design law.invention Application-specific integrated circuit Chip-scale package law Embedded system Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering Crossbar switch business Software Hardware_LOGICDESIGN |
| Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29:2046-2050 |
| ISSN: | 1937-4151 0278-0070 |
| DOI: | 10.1109/tcad.2010.2063111 |
| Popis: | In recent years, structured application-specific integrated circuit (ASIC) design style has lessened the importance of mask cost. Multiple structured ASIC chip designs share the same pre-fabricated device and wire masks. Nevertheless, the interconnection delay in a pre-fabricated wire slows down circuit performance as a result of high capacitive load. We propose a dual-rail routing architecture that reduces wire delay by 10% to 15% compared to the original routing architecture. Furthermore, we propose a dual-rail insertion algorithm to reduce routing area overhead. The experimental results demonstrate that our dual-rail technique reduces wire delay by 9.8% with 4.8% routing area overhead and improves overall circuit performance by 7.0%. |
| Databáze: | OpenAIRE |
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