| Autor: |
Mills Duane R, Tomohito Tsushima, Kirk D. Prall, Jahanshir Javanifard, Keiichi Tsutsui, Glen E. Hush, Fackenthal Richard E, Makoto Kitagawa, Wataru Otsuka, Kerry Dean Tedrow, Yoshiyuki Shibahara |
| Rok vydání: |
2014 |
| Předmět: |
|
| Zdroj: |
ISSCC |
| DOI: |
10.1109/isscc.2014.6757460 |
| Popis: |
Resistive RAMs (ReRAMs) have emerged as leading candidates to displace conventional Flash memories due to their high density, good scalability, low power and high performance. Previous ReRAM designs demonstrating high performance have done so on low density arrays ( 8Gb) were accompanied by relatively low read and write performance [1-5]. This work describes a 16Gb ReRAM designed in a 27nm node, with a 1GB/s DDR interface and an 8-bank concurrent DRAM-like core architecture. High parallelism, a pipelined data-path architecture and innovations such as concurrent set/reset verify combine to achieve 200MB/s write and 1GB/s read throughputs in a high-density device. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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