An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface

Autor:	Manish Jain, Phuong Le, Navin Kumar Mishra, Amir Amirkhany, Sanku Mukherjee, Arul Sendhil
Rok vydání:	2011
Předmět:	Memory interface Engineering Bi modal business.industry Capacitive sensing Interface (computing) Electronic engineering Equalization (audio) business Energy (signal processing) Dram
Zdroj:	CICC
Popis:	A bi-modal x32 memory interface supports 6.4-Gbps GDDR5 signaling as well as 2.4-Gbps DDR3 signaling with a 1.5V IO supply. The interface incorporates a novel driver and pre-driver structure that supports one-tap equalization and presents very small capacitive loading to the pins. The entire interface, including both data and request channels achieves 11.6mW/Gbps and 27.7mW/Gbps energy efficiencies in GDDR5 and DDR3 modes respectively, and communicates successfully with 1.6-Gbps DDR3 and 6.0-Gbps GDDR5 DRAMs.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::c8932f86f0d7be9967632f0f87ffde82 https://doi.org/10.1109/cicc.2011.6055399 Zobrazit plný text záznamu