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This paper analyzes aging effects on various design hierarchies of a sub-45nm commercial processor running realistic applications. Dependencies of aging effects on switching-activity and power-state of workloads are quantified. This paper presents an “instance-based” simulation flow, which creates a standard-cell library for each use of the cell in the design, by aging each transistor individually. Implementation results show that processor timing degradation can vary from 2% to 11%, depending on workload. Lifetime computational power efficiency improvements of optimized self-tuning is demonstrated, relative to a one-time worst-case guardbanding approach. |
