| Autor: |
Albert Au, Ashok Anbalan, Jean-Francois Cote, Luc Romain, Banadappa Shivaray, Suresh Raman, Venkat Yellapragada, Benoit Nadeau-Dostie, Giri Podichetty, Martin Keim |
| Rok vydání: |
2018 |
| Předmět: |
|
| Zdroj: |
ITC-Asia |
| DOI: |
10.1109/itc-asia.2018.00018 |
| Popis: |
A tile based design methodology consists of developing design blocks that are inserted in design layouts by placing blocks next to each other, making a tile-to-tile connection by abutting corresponding physical signal lines at the border of the tile. Very large systems can be easily and rapidly developed by seamlessly integrating tile elements in the layout. Further, the ease of top-level integration underlines the advantages over a bottom-up approach. However, this tile-based approach is incompatible with traditional DFT tools, which were created to work in accordance with the bottom-up design methodology. This paper outlines some of the obstacles to overcome, to support a truly tile-based DFT methodology. We describe here a working solution for a large production design, underlining a successful implementation of a tile-based Memory Test methodology. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
|
