| Popis: |
The analog implementation of error control decoders is a power efficiency and speed competitive methodology comparing with the digital implementation. In this paper, we propose a mixed behavioral/structural model for the analog implementation of low-density parity-check (LDPC) decoders based on the sum-product algorithm, while taking transistor mismatch effects and circuit dynamic behavior into account. The model, relating transistor-level parameters to system-level specifications, can be used for both estimating the system performance of the analog decoders and providing circuit-optimization guidelines for complex decoder. The model is applied to a (40, 16) linear block code and simulation results demonstrated the model can reliably predict the system performance in a short time. |
