Impacts of device architecture and low current operation on resistive switching of HfOx nanoscale devices
| Autor: | Wei-Su Chen, Frederick T. Chen, Chen-Han Tsai, Pang-Shiu Chen, Heng-Yuan Lee, Tai-Yuan Wu, Yu-Sheng Chen, Pei-Yi Gu, Ming-Jinn Tsai, Kan-Hsueh Tsai |
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| Rok vydání: | 2013 |
| Předmět: |
Materials science
Dielectric strength business.industry Transistor Nanotechnology Condensed Matter Physics Atomic and Molecular Physics and Optics Surfaces Coatings and Films Electronic Optical and Magnetic Materials law.invention Resistive random-access memory Parasitic capacitance law Overshoot (signal) Optoelectronics Electrical and Electronic Engineering Current (fluid) business Scaling Voltage |
| Zdroj: | Microelectronic Engineering. 105:40-45 |
| ISSN: | 0167-9317 |
| DOI: | 10.1016/j.mee.2012.12.012 |
| Popis: | A highly scaling feasibility of resistance memory with a via-hole structure including Ti/HfO"x is demonstrated in this work. An empirical model is used to predict the correlation between the forming voltage of 5nm-thick HfO"x devices with concave configuration and their cell size. The forming voltage of the nano-devices fit well with the empirical model of dielectric breakdown. Owing to the parasitic capacitance of the support oxide, the resistance memory with a series transistor still suffers a serious current overshoot during the forming process. The first reset current in the concave device increase as the scaling down of their cell size. The 30nm concave device with a compliance current of 0.18mA exhibits a good operation window (ON/OFF resistance ratio >30), a satisfactory reliabilities including a thermal stability at 150^oC for 500min lifetime and switching cycles of 10^4. The operation current for 50nm concave device can be lowered to 30@mA. The first reset current in the pillar device through increasing the dielectric thickness in the parasitic capacitance can be eliminated. |
| Databáze: | OpenAIRE |
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