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Quantum key distribution (QKD) gives a way to generate unconditionally secure keys for two remote users, Alice and Bob. Information reconciliation (IR), which can correct the errors caused by the imperfections of the QKD systems, is a critical component in QKD. Due to the high-security requirements and large volumes of data processing, robustness and efficiency are two main factors that must be considered for the implementation of IR. The polar codes-based IR has several potential advantages, such as capacity to reach Shannon-limit, high IR efficiency, and low computational complexity. Although CPU-based IR is always implemented in most of the previous works, it is not the optimal implementation in terms of performance and power dissipation. To the best of our knowledge, there is still no work to build a special-purpose hardware module for polar codes-based IR. In this paper, a dedicated design of hardware accelerator is first proposed for polar codes-based IR, in which the block-checked successive cancellation list (SCL) algorithm is used to verify the consistency of the sifted keys, and the overall failure probability of IR is significantly reduced. The proposed design is constructed into a partially-unrolled parallel architecture to accelerate the core decoder as well as balance the resource utilization. Furthermore, the hardware implementation is completed based on Xilinx Zynq UltraScale+ XCZU5EV MPSoC platform and achieves an IR throughput of 15 Mbps with a block length of 212, while less than 20 % of the amount of on-chip resources are used in other previous designs of SCL decoder. The proposed design can provide a real-time, low-cost solution for IR in QKD systems, and enhance the performance of QKD. |
