A monolithic vernier-based time-to-digital converter with dual PLLs for self-calibration

Autor:	Jia-Chi Zheng, Chun-Chi Chen, Poki Chen
Rok vydání:	2006
Předmět:	Engineering Vernier scale business.industry Converters Line (electrical engineering) law.invention Time-to-digital converter Phase-locked loop Least significant bit CMOS law Hardware_INTEGRATEDCIRCUITS Calibration Electronic engineering business
Zdroj:	CICC
DOI:	10.1109/cicc.2005.1568670
Popis:	This paper presents a monolithic vernier-based time-to-digital converter with 37.5 ps time resolution and theoretically unlimited input range. A single-stage Vernier delay line is used for both coarse and fine measurement. The operation frequencies of Vernier delay line are stabilized by a novel dual phase-locked loops circuit. The proposed TDC successfully eliminates the element mismatch, input range limitation, external bias adjustment and complicated calibration problems. The measured DNL and INL are plusmn0.2 LSB and plusmn0.35 LSB respectively. The chip size is merely 0.222mm2 in a 0.35-mum CMOS process
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::c7183d5256956aaa782b2e044ffc24ab https://doi.org/10.1109/cicc.2005.1568670 Zobrazit plný text záznamu