Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process

Autor:	Fu-Yi Tsai, Chia-Tsen Dai, Po-Yen Chiu, Yan-Hua Peng, Ming-Dou Ker, Chia-Ku Tsai
Rok vydání:	2012
Předmět:	Engineering Electrostatic discharge Clamp CMOS business.industry Clamper Logic gate Electrical engineering business Transmission-line pulse Electronic circuit Voltage
Zdroj:	2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.
DOI:	10.1109/ipfa.2012.6306283
Popis:	The ESD robustness of gate-driven ESD clamp circuit in a 16-V CMOS process was investigated by the stresses of transmission line pulse (TLP), human-body-model ESD test, and machine-model (MM) ESD test. After TLP stresses of different voltage steps, the same ESD clamp circuit got different secondary breakdown currents (It2). In order to understand such unusual phenomenon, the failure analysis on the TLP-stressed ESD clamp circuits was performed to find the failure mechanism.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::c6f9b0b857a7c0d836a14805654ca4b2 https://doi.org/10.1109/ipfa.2012.6306283 Zobrazit plný text záznamu