| Autor: |
Ilyas Elkin, Mamun Rashid, I. Parulkar, M. Steigerwald, Yuefei Ge, S. Gundala, Peter F. Lai, Y. Otaguro, Leonard D. Rarick, Rambabu Pyapali, Y. Orginos, Georgios Konstadinidis, S. Parampalli |
| Rok vydání: |
2008 |
| Předmět: |
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| Zdroj: |
ISSCC |
| DOI: |
10.1109/isscc.2008.4523068 |
| Popis: |
This third-generation chip-multithreading (CMT) SPARC processor is targeted for high-performance servers, and is optimized for both single- and multi-threaded applications. The architecture highlights are provided in [M. Tremblay and S. Chaudhry, 2008], while this paper focuses on the physical implementation aspects, providing an overview of circuit innovations in memory arrays, register files, and floating-point hardware that boost the performance and circuit robustness with low area overhead. The 396mm2 chip is fabricated in a 11M 65nm CMOS process and operates at a nominal frequency of 2.3GHz, consuming a maximum power of 250W at 1.2V. Power-management techniques include clock gating at core-cluster level and power throttling through a single-thread-issue mode of operation. This mode is used in power-constrained systems without sacrificing single-thread performance. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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