100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet
| Autor: | Hiroaki Nishi, Michitaka Okuno, Kouji Nakahara, Kouji Fukuda, Hidehiro Toyoda, Shinji Nishimura |
|---|---|
| Rok vydání: | 2006 |
| Předmět: |
Metropolitan area network
Ethernet Optical fiber Computer Networks and Communications business.industry Computer science Physical layer Throughput law.invention Transmission (telecommunications) law Wavelength-division multiplexing Bit error rate Electrical and Electronic Engineering business Telecommunications Software Computer hardware Data transmission |
| Zdroj: | IEICE Transactions on Communications. :696-703 |
| ISSN: | 1745-1345 0916-8516 |
| DOI: | 10.1093/ietcom/e89-b.3.696 |
| Popis: | A high-speed physical-layer architecture for Ethernet is described that supports 100-Gb/s throughput and 40-km transmission, making it well suited for next-generation metro-area and intrabuilding networks. Its links comprise 12 x 10-Gb/s synchronized parallel optical lanes. Ethernet data frames are transmitted by coarse wavelength division multiplexing link and bundled optical fibers. Ten of the lanes convey 640-bit data synchronously (64 bits x 10 lanes). One conveys forward error correction code ((132b, 140b) Hamming code), providing highly reliable (BER < 10 -12 ) data transmission, and the other conveys parity data, enabling faultlane recovery. A newly developed 64B/66B code-sequence-based deskewing mechanism is used that provides low-latency compensation for the lane-to-lane skew, which is less than 88 ns. Testing of this physical-layer architecture in a field programmable gate array circuit demonstrated that it can provide 100-Gb/s data communication with a 590k gate circuit, which is small enough for implementation in a single LSI circuit. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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