| Autor: |
Chin Lee Kuan, Amit K. Jain, Sameer Shekhar |
| Rok vydání: |
2017 |
| Předmět: |
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| Zdroj: |
2017 IEEE 19th Electronics Packaging Technology Conference (EPTC). |
| DOI: |
10.1109/eptc.2017.8277498 |
| Popis: |
With modern low power circuits needing supply voltages around 0.6 [V], there is a growing need for accurately accounting for DC variations. To accentuate the problem proliferation of power supplies for extended battery life has forced tightly co-located voltage regulators which can easily see 20–50 [mV] variation on common ground plane. Independent analysis of loads therefore can lead to suboptimal power and performance estimates. This paper presents analysis and design methodology to study DC interaction of input and output network for power converters to accurately account for spatial distribution of current and the resulting potential differences. The contribution also enables important design aspects such as sense point optimization and PCB & package layout bottleneck identification. Paper documents design of a 1 [V] output buck voltage regulator with 4% output voltage spread for illustration. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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