Low-power 2K-cell SDFL gate array and DCFL circuits using GaAs self-aligned E/D MESFETs
| Autor: | G. Y. Lee, K.W. Lee, S.A. Hanka, C.A. Arsenault, Barry K. Gilbert, Andrzej Peczalski, Michael Shur, M.J. Helix, S.A. Jamison, W.R. Betten, S.M. Karwoski, Roderick D. Nelson, P.C.T. Roberts, Tho T. Vu, S.K. Swanson, G.M. Lee, P.J. Vold, B.A. Naused |
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| Rok vydání: | 1988 |
| Předmět: |
Adder
Materials science business.industry Clock rate Electrical engineering Schottky diode Hardware_PERFORMANCEANDRELIABILITY Integrated circuit law.invention Gate array law Logic gate Hardware_INTEGRATEDCIRCUITS Field-effect transistor Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering business Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | IEEE Journal of Solid-State Circuits. 23:224-238 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/4.283 |
| Popis: | Using GaAs self-aligned gate MESFETs, low-power logic circuits have been demonstrated for both depletion-mode (D-mode) Schottky-diode FET logic (SDFL) and enhancement/depletion-mode (E/D-mode) direct-coupled FET logic (DCFL). Propagation delays of 1.6 ns have been obtained for SDFL operating are 108 mu W per gate. DCFL has demonstrated ring-oscillator gate delays of 30 ps and speed-power products as low as 1.1 fJ per gate. A 2K-cell gate array designed with low-power SDFL has demonstrated an 8-bit adder with an add time of 11 ns at 236 mW. Automatic software was used for the placement and routine of the 8-bit adder in the gate array. DCFL divide-by-four circuits designed for 500-MHz operation have demonstrated up to 2.5-GHz operation with a power dissipation of 172 mu W per gate at 1-GHz clock frequency. DCFL divide-by-four circuits subjected to 3.4*10/sup 7/ rads (Si) and 1*10/sup 14/ N/cm/sup 2/, for total dose and neutron fluence, respectively, have demonstrated only minimal reduction in power and no degradation of circuit performance. > |
| Databáze: | OpenAIRE |
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