| Autor: |
Seung-Hee Yang, Jae-Whui Kim, Hyun-goo Kim, Jongshin Shin, Jiyoung Kim, Jongjae Ryu, Bongjin Kim, Chi-Won Kim, Jae-Hyun Park |
| Rok vydání: |
2008 |
| Předmět: |
|
| Zdroj: |
CICC |
| DOI: |
10.1109/cicc.2008.4672067 |
| Popis: |
A 65 nm HDMI TX PHY was designed with supply-regulated dual-tuning PLL and blending multiplexer. The proposed PLL uses a new dual-tuning scheme for small capacitor and low-jitter while keeping the supply regulation capability. A fractional-N operation for non-integer pixel clock generation was implemented with a blending multiplexer which enables seamless switching of high-speed multiphase clock. The fabricated PHY gives maximum 3.4 Gbps data rate per channel and shows 34 ps peak-to-peak data jitter. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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