A 2GHz, 7W (max) 64b PowerTM Microprocessor Core

Autor:	A. Radhakrishnan, M. Chung, N. Nerurkar, Fang Liu, Y. Modukuru, F. Klass, B. Fernandes, Brian J. Campbell, J. Yong, S. Sundar, Zhibin Huang, A. Mehta, D. Murray, S. Ghosh, E. Wu, P. Kanapathipillai, H.J. Tarn, Hang Huang, Rajat Goel, J. Burnette, G. Hess, N. Javarappa, S. Santhanam, Jung-Cheng Yeh, R. Wen, Junji Sugisawa, S. Zambare
Rok vydání:	2007
Předmět:	Adiabatic circuit Computer science Mixed-signal integrated circuit Hardware_PERFORMANCEANDRELIABILITY Integrated circuit Power optimization law.invention Microprocessor Integrated injection logic CMOS law Hardware_INTEGRATEDCIRCUITS Electronic engineering Electrical efficiency Hardware_LOGICDESIGN
Zdroj:	CICC
DOI:	10.1109/cicc.2007.4405833
Popis:	The PA6T core is an out-of-order superscalar implementation of the power architecture. Power efficiency is achieved through micro-architecture, logic, and circuit optimizations. The processor is fabricated in a 65 nm, triple Vt, dual oxide 8 M CMOS process. Worst-case power dissipation at 2 GHz is 7 W.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::c42152cef3c4227008064ae69d721d61 https://doi.org/10.1109/cicc.2007.4405833 Zobrazit plný text záznamu