Test Clock Domain Optimization to Avoid Scan Shift Failure Due to Flip-Flop Simultaneous Triggering
| Autor: | Min-Hong Tsai, James Chien-Mo Li, Hung-Chun Li, Ming-Tung Chang, Chih-Mou Tseng, Wei-Sheng Ding, Yu-Chiuan Huang, Min-Hsiu Tsai |
|---|---|
| Rok vydání: | 2013 |
| Předmět: |
Speedup
Computer science Design for testing Scan chain Parallel algorithm Test compression Hardware_PERFORMANCEANDRELIABILITY Computer Graphics and Computer-Aided Design law.invention law Benchmark (computing) Electronic engineering Electrical and Electronic Engineering Algorithm Software Flip-flop Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32:644-652 |
| ISSN: | 1937-4151 0278-0070 |
| DOI: | 10.1109/tcad.2012.2228741 |
| Popis: | This paper presents a design for testability technique to avoid scan shift failure due to flip-flop simultaneous triggering. The proposed technique changes test clock domains of flip-flops in the regions where severe IR-drop problems occur. A massive parallel algorithm using a graphic processor unit is adopted to speed up the IR-drop simulation during optimization. The experimental data on large benchmark circuits show that peak IR-drop values are reduced by 15% on average compared with the circuit after simple MD-SCAN partition. Our proposed technique quickly optimizes a half-million-gate design within two hours. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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