The Impact of Strain Technology on FUSI Gate SOI CMOSFET
| Autor: | Wen-Kuan Yeh, Po-Ying Chen, Jean-An Wang, Ming-Hsing Tsai, Chien-Ting Lin |
|---|---|
| Rok vydání: | 2009 |
| Předmět: |
Materials science
business.industry Capacitive sensing Electrical engineering Silicon on insulator Noise (electronics) Electronic Optical and Magnetic Materials Strain engineering Reliability (semiconductor) CMOS MOSFET Optoelectronics Electrical and Electronic Engineering Safety Risk Reliability and Quality business Voltage |
| Zdroj: | IEEE Transactions on Device and Materials Reliability. 9:74-79 |
| ISSN: | 1558-2574 1530-4388 |
| DOI: | 10.1109/tdmr.2008.2010622 |
| Popis: | In this paper, the impact of strain engineering on device performance and reliability for fully silicide gate silicon-on-insulator CMOSFET was investigated. With characterizing device's electrical property after hot carrier (HC) and positive/negative bias instability voltage stressing, we found similar enhancement on device performance but different behavior on voltage-stressing-induced device degradation for n/pMOSFETs. Related noise analysis and charge pumping techniques were used to investigate the strain-induced oxide defect which will accelerate device degradation after long-time HC voltage stressing and/or bias instability voltage stressing. |
| Databáze: | OpenAIRE |
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