New activity-driven clock tree design methodology for low power clock gating
| Autor: | Jia-Hong Jian, Shih-Hsu Huang, Chen-Hsien Lin, Xin-Jia Chen |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Synchronous circuit
Clock signal Computer science 020208 electrical & electronic engineering Clock gating 02 engineering and technology Digital clock manager Clock skew 020202 computer hardware & architecture Clock domain crossing 0202 electrical engineering electronic engineering information engineering Electronic engineering Asynchronous circuit CPU multiplier |
| Zdroj: | 2017 6th International Symposium on Next Generation Electronics (ISNE). |
| Popis: | Clock gating is a useful technique to reduce power consumption of a synchronous sequential circuit. Conventionally, we use activity patterns, which are derived from a scheduled data flow graph and a module binding solution, to represent enable logics for clock gating. Based on activity patterns of modules, previous works utilize AND gates to construct activity-driven clock trees. In this paper, we demonstrate that, if we utilize OR gates at the bottom level, the power consumption at higher levels can be greatly reduced. From this observation, we propose a novel activity-driven clock tree design methodology, including a new tree structure and a corresponding design flow. Benchmark data show that our methodology can reduce 7.1% clock power consumption. |
| Databáze: | OpenAIRE |
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