Modeling for Spin-FET and Design of Spin-FET-Based Logic Gates
| Autor: | Weisheng Zhao, Jacques-Olivier Klein, Zhaohao Wang, Gefei Wang |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Diode logic
Diode–transistor logic Pass transistor logic Computer science Semiconductor device modeling Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology 01 natural sciences PMOS logic law.invention Computer Science::Emerging Technologies law 0103 physical sciences Hardware_INTEGRATEDCIRCUITS Electronic engineering Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering NMOS logic Electronic circuit Spin-½ Register-transfer level 010302 applied physics Digital electronics Spintronics business.industry Transistor Logic family NOR logic Emitter-coupled logic Condensed Matter::Mesoscopic Systems and Quantum Hall Effect 021001 nanoscience & nanotechnology Resistor–transistor logic Electronic Optical and Magnetic Materials Tunnel magnetoresistance Semiconductor Logic synthesis Integrated injection logic Logic gate Inverter Condensed Matter::Strongly Correlated Electrons 0210 nano-technology business AND gate Hardware_LOGICDESIGN |
| Zdroj: | IEEE Transactions on Magnetics. 53:1-6 |
| ISSN: | 1941-0069 0018-9464 |
| Popis: | Spintronics-based devices and circuits attract massive research interest from both academia and industry. A number of the devices and logic circuits have been proposed such as spin-based magnetic tunnel junction and all spin logic gate. A fundamental spin-based device, spin field-effect transistor (spin-FET) is one of the most interesting spin-based devices to address the power issue of semiconductor transistors which is still a research focus. In this paper, we first present an electrical model for the spin-FET based on both theoretical and experimental results. The theories of spin injection and detection are considered by a current driver of the spin-FET. Gate voltage modulation following Datta–Das theory is combined with the experimental results from several works of literature. Afterward, through the dc analysis of two spin-FETs with different channel materials, we demonstrate that the channel using InAs is a better choice to make a feasible spin-FET. The channel length is also optimized by the comparison of simulation results. Finally, a local geometry spin-FET model suitable for logic design is implemented with Verilog-A language and integrated on Cadence platform. Using our model, a low-power inverter is designed based on the concept of complementary spin-FET, and a logic circuit is proposed to implement AND and NOR logic functions. Simulation results validate the behaviors of the logic circuits and availability of our model. |
| Databáze: | OpenAIRE |
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