A $\Delta\Sigma$ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth
| Autor: | Junyoung Song, Chulwoo Kim, Sewook Hwang, Yeonho Lee, Sang-Geun Bae |
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| Rok vydání: | 2019 |
| Předmět: |
Physics
020208 electrical & electronic engineering 020206 networking & telecommunications 02 engineering and technology Delta-sigma modulation Topology Electromagnetic interference Phase-locked loop CMOS EMI 0202 electrical engineering electronic engineering information engineering Clock generator Electrical and Electronic Engineering Frequency modulation Jitter |
| Zdroj: | IEEE Transactions on Circuits and Systems II: Express Briefs. 66:192-196 |
| ISSN: | 1558-3791 1549-7747 |
| Popis: | A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip without shielding the device that increases the system cost and weight. In a ${\Delta } {\Sigma }$ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the phase-locked loop bandwidth ( $ {f}_{{\text {LBW}}}$ ). This brief proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of $ {f}_{\text {LBW}}$ variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest $ {f}_{\text {LBW}}$ . A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292 mm2. |
| Databáze: | OpenAIRE |
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