Low power VLSI architecture for combined FMO/Manchester encoder for reusability and FMO/Manchester codecs
| Autor: | M. Sumanth, Sonali Agrawal, K. Sai Sandeep, N. Sowjith |
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| Rok vydání: | 2016 |
| Předmět: |
business.industry
Computer science 010401 analytical chemistry Real-time computing Transistor 01 natural sciences 0104 chemical sciences law.invention CMOS law Encoding (memory) Logic gate Hardware_INTEGRATEDCIRCUITS Codec business Encoder Computer hardware Decoding methods Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | 2016 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC). |
| Popis: | The VLSI architecture for the low power combined FM0 and Manchester encoder (SOLS) circuit using modified GDI has been proposed in this paper. Comparisons are made with existing architecture using general CMOS Logic. The power consumption and delay in this circuit are reduced. The working conditions for existing circuit for FMO/Manchester encoder and decoder using HCPM technique have also been modified in this paper. The architecture has been realized in CMOS 90 nm technology. Cadence Virtuoso Analog design environment has been used for implementing and synthesizing the test circuits. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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