Autor: Rafael Domínguez-Castro, G. Linan, Servando Espejo, Ángel Rodríguez-Vázquez
Rok vydání: 2002
Předmět:
Zdroj: Analog Integrated Circuits and Signal Processing. 33:179-190
ISSN: 0925-1030
DOI: 10.1023/a:1021272100265
Popis: From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35 µm standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (~7 bits) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330 GOPs (Giga Operations per second), and uses the power supply (180 GOP/Joule) and the silicon area (3.8 GOPS/mm2) efficiently, and is able to maintain VGA processing throughputs of 100 Frames/s with about 1020 basic image processing tasks on each frame.
Databáze: OpenAIRE