DC-30 GHz DPDT Switch Matrix Design in High Resistivity Trap-Rich SOI
| Autor: | Kaixue Ma, Parthasarathy Shyam, Fanyi Meng, Bo Yu, Shaoqiang Zhang, Purakh Raj Verma, Kiat Seng Yeo |
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| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Materials science business.industry Bandwidth (signal processing) Transistor Electrical engineering Silicon on insulator 020206 networking & telecommunications 02 engineering and technology Chip 01 natural sciences Electronic Optical and Magnetic Materials law.invention law Logic gate 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Insertion loss Electrical and Electronic Engineering Crossover switch Wideband business |
| Zdroj: | IEEE Transactions on Electron Devices. 64:3548-3554 |
| ISSN: | 1557-9646 0018-9383 |
| DOI: | 10.1109/ted.2017.2725485 |
| Popis: | This paper presents low insertion loss, high isolation, ultra-wideband double-pole-double-throw (DPDT) switch matrix designed in a 0.13- $\mu \text{m}$ commercial high resistivity trap-rich silicon-on-insulator (SOI) CMOS process for the first time. The switches are designed using series–shunt–series configuration in a ring-type structure with input and output matching networks. Transistor width and transistor channel length effects on the wideband DPDT switch performance are thoroughly investigated. The designed switches achieve widest bandwidth from dc to 30 GHz with a low insertion loss of 2.5 dB and a high isolation of 32 dB up to 30 GHz. The measured input P1dB of designed switches is higher than 18 dBm. It was found both second and third harmonics can be improved by widening switch transistor channel width, and third harmonic can be improved by shortening channel length. The active chip area of designed $2 \times2$ switch matrix is very small size of only 0.28 mm $\times0.21$ mm. |
| Databáze: | OpenAIRE |
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