Flexible hardware approach to multi‐core time‐predictable systems design based on the interleaved pipeline processing
| Autor: | Andrzej Pulka, Ernest Antolak |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Multi-core processor Reduced instruction set computing business.industry Computer science Pipeline (computing) 020208 electrical & electronic engineering 02 engineering and technology 01 natural sciences Control and Systems Engineering Multithreading 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Systems architecture Systems design Verilog Electrical and Electronic Engineering business Field-programmable gate array computer Computer hardware computer.programming_language |
| Zdroj: | IET Circuits, Devices & Systems. 14:648-659 |
| ISSN: | 1751-8598 1751-858X |
| DOI: | 10.1049/iet-cds.2019.0521 |
| Popis: | The study presents a hardware-based approach to modelling and design of time-predictable electronic embedded systems. It addresses multithread and multitask problems of contemporary real-time systems. Authors propose a universal template of the reconfigurable system architectures that can be flexibly accommodated to a given application. The synthesisable and parametrised model of the system architecture has been implemented in VERILOG. The architecture is based on ARM-like RISC solutions and its heart, the main core, is built of 8–12 stage reconfigurable pipelining with the interleaving mechanism. This core is a basic building block of the system and it can be replicated. Each core can handle several hardware threads with replicated register files. The entire structure has a deadline controlling mechanism that is responsible for tasks' evaluation predictability. The authors analyse the coherency of the proposed memory system and interoperability between hardware threads. Three different static scheduling algorithms have been developed and presented in examples. This study contains the results of the simulation experiments and the summary of the hardware implementation in Virtex-7 FPGA platforms. Authors have investigated the timing parameters of the system and pointed out the areas for further research. |
| Databáze: | OpenAIRE |
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