A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy
| Autor: | Li Fule, Xu Lili, Zhou Jia, Wang Zhihua |
|---|---|
| Rok vydání: | 2015 |
| Předmět: |
business.industry
Computer science Page layout Pipeline (computing) Successive approximation ADC Hardware_PERFORMANCEANDRELIABILITY Condensed Matter Physics computer.software_genre Electronic Optical and Magnetic Materials Bit (horse) CMOS Hardware_INTEGRATEDCIRCUITS Materials Chemistry Electronic engineering Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering business Scaling Digital converter computer Computer hardware Communication channel |
| Zdroj: | Journal of Semiconductors. 36:085008 |
| ISSN: | 1674-4926 |
| Popis: | A 10 bit, 120 MS/s two-channel pipelined analog-to digital converter (ADC) is presented. The ADC is featured with improved switch by using the body effect to improve its conduction performance. A scaling down strategy is proposed to get more efficiency in the OTAs layout design. Implemented in a 0.18-μm CMOS technology, the ADC's prototype occupied an area of 2.05 × 1.83 mm2. With a sampling rate of 120-MS/s and an input of 4.9 MHz, the ADC achieves a spurious-free-dynamic range of 74.32 dB and signal-to-noise-and-distortion ratio of 55.34 dB, while consuming 220-mW/channel at 3-V supply. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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