Versatile SoC architecture for integration of HW accelerators in power electronics applications
| Autor: | Edel Diaz Llerena, Raul Mateos Gil, Daniel Calvo Guillen, Javier Pavon Luque |
|---|---|
| Rok vydání: | 2021 |
| Předmět: |
Computer science
business.industry Maintainability 020206 networking & telecommunications 02 engineering and technology Modular design Control system Embedded system Power electronics Scalability 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing Architecture business Field-programmable gate array Reusability |
| Zdroj: | ICIT |
| Popis: | The use of high-level synthesis (HLS) tools for HW implementation of control algorithms has become very popular in power converter applications. This work presents a versatile SoC architecture for integrating HLS-generated HW accelerators in power electronics applications. The novel proposal uses a Hub-based architecture that controls the execution of multiple HW accelerators. The Hub-based architecture provides an improved development, maintainability, scalability, and reusability of HW accelerators compared to the typical monolithic approach. Besides, it offers the possibility to split and parallelize them to achieve a modular design. This architecture has been validated using a real application (battery charger) as a case study. The new proposal does not significantly increase the logic of resource consumption in the FPGA. The case above study also reduces the latency by more than 50% compared with a single monolithic IP used to implement the control algorithm. |
| Databáze: | OpenAIRE |
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