Leakage current aware high-level estimation for VLSI circuits
| Autor: | Fei Li, Rakesh J. Patel, J.M. Basile, Lei He, Hema Ramamurthy |
|---|---|
| Rok vydání: | 2005 |
| Předmět: |
Very-large-scale integration
Adder Engineering Power gating business.industry Hardware_PERFORMANCEANDRELIABILITY Circuit reliability Theoretical Computer Science Logic synthesis Computational Theory and Mathematics Hardware and Architecture MOSFET Hardware_INTEGRATEDCIRCUITS Electronic engineering Full custom business Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | IEE Proceedings - Computers and Digital Techniques. 152:747 |
| ISSN: | 1350-2387 |
| DOI: | 10.1049/ip-cdt:20045165 |
| Popis: | The ever-growing leakage current of MOSFETs in nanometre technologies is the major concern to high performance and power efficient designs. Dynamic power management via power-gating is effective to reduce leakage power, but it introduces power-up current that affects the circuit reliability. The authors present an in-depth study on high-level modelling of power-up current and leakage current in the context of a full custom design environment. They propose a methodology to estimate the circuit area, maximum power-up current, and minimum and maximum leakage current for any given logic function. Novel estimation metrics are built based on logic synthesis and gate-level analysis using only a small number of typical circuits, but no further logic synthesis and gate-level analysis are needed during the high-level estimation. Compared to time-consuming logic synthesis and gate-level analysis, the average errors for circuits from a leading industrial design project are 23.59% for area, 21.44% for maximum power-up current, 15.65% for maximum leakage current and 6.21% for minimum leakage current. In contrast, estimation based on quick synthesis leads to an 11× area difference in gate count for an 8-bit adder. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|