| Autor: |
Ji Hye Yi, Hwa-Sung Rhee, Sun Me Lim, Moon Han Park, Hoi-sung Chung, Nae-In Lee, Yong Shik Kim, J.S. Yoon, Myung Sun Kim, Min Sun Kim, Ho Lee |
| Rok vydání: |
2008 |
| Předmět: |
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| Zdroj: |
2008 IEEE International Electron Devices Meeting. |
| DOI: |
10.1109/iedm.2008.4796849 |
| Popis: |
We have successfully reduced threshold voltage variation by combination of co-implantation and laser spike anneal on 45 nm low power SoC platform with conventional poly-Si/SiON gate stack. Doping profiles of CMOSFET channel is modulated through co-implantation of diffusion suppressor. We have explored the possibility of cluster carbon doping in order to minimize junction leakage degradation. Systematic junction profile design for n- and pFET enables us to reduce random dopant variation significantly without compromising standby leakage, drive current and gate oxide integrity, which finally contributes to RO ~5% performance improvement at equivalent Iddq and ensures high yield of SRAM array by reducing beta and gamma ratio variation. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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