Comparison of Level Shifter Architectures: Application to I/O Cell
| Autor: | Radu-Valentin Petrica, Philippe Coll, Mihaela-Daniela Dobre, Florin Draghici, Gheorghe Brezeanu |
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| Rok vydání: | 2018 |
| Předmět: |
0301 basic medicine
Silicon Computer science Transistor chemistry.chemical_element Topology (electrical circuits) Logic level Network topology law.invention 03 medical and health sciences 030104 developmental biology 0302 clinical medicine chemistry law Logic gate Hardware_INTEGRATEDCIRCUITS Electronic engineering Reference architecture 030217 neurology & neurosurgery Electronic circuit |
| Zdroj: | 2018 International Semiconductor Conference (CAS). |
| DOI: | 10.1109/smicnd.2018.8539796 |
| Popis: | Novel low-voltage and high-speed level shifter topologies will be presented. The level shifters circuits were designed in 40 nm technology using 1.2V devices and zero-VT transistors. These techniques will provide functionality near the threshold region. The simulated results were compared with a reference architecture. The resulted level shifters will be integrated in an already tested I/O structure. The results were analyzed in terms of electrical performance and silicon area. |
| Databáze: | OpenAIRE |
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