A full E-beam 0.25 mu m bipolar technology with sub-25 ps ECL gate delay
| Autor: | K.N. Chiong, Denny D. Tang, F.J. Hohn, James D. Warnock, P.J. Coane, E. Petrillo, J.Y.-C. Sun, M.G.R. Thomson, John D. Cressler, N.J. Mazzeo, M.E. Rothwell, Keith A. Jenkins, A.E. Megdanis, Joachim N. Burghartz |
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| Rok vydání: | 2002 |
| Předmět: |
Materials science
Pass transistor logic business.industry Heterostructure-emitter bipolar transistor Transistor Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Emitter-coupled logic Resistor–transistor logic law.invention Integrated injection logic law Hardware_INTEGRATEDCIRCUITS business Lithography Electron-beam lithography Hardware_LOGICDESIGN |
| Zdroj: | International Electron Devices Meeting 1991 [Technical Digest]. |
| DOI: | 10.1109/iedm.1991.235267 |
| Popis: | Summary form only given. The full leverage offered by E-beam lithography has been exploited in a 0.25- mu m bipolar process. The tight overlay capability was shown to provide a significant advantage in shrinking the overall transistor size. In conjunction with a device technology optimized to provide a 33-GHz 0.25- mu m-emitter device, this culminated in the achievement of an ECL (emitter coupled logic) delay of 24 ps at a switching current of only 1.1 mA. > |
| Databáze: | OpenAIRE |
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