Low-Cost Thin Glass Interposers as a Superior Alternative to Silicon and Organic Interposers for Packaging of 3-D ICs
| Autor: | Tapobrata Bandyopadhyay, Rao Tummala, Vijay Sukumaran, Venky Sundaram |
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| Rok vydání: | 2012 |
| Předmět: |
Materials science
Silicon business.industry chemistry.chemical_element Substrate (electronics) Integrated circuit Industrial and Manufacturing Engineering Electronic Optical and Magnetic Materials law.invention Printed circuit board chemistry law Miniaturization Interposer Electronic engineering Optoelectronics Wafer Integrated circuit packaging Electrical and Electronic Engineering business |
| Zdroj: | IEEE Transactions on Components, Packaging and Manufacturing Technology. 2:1426-1433 |
| ISSN: | 2156-3985 2156-3950 |
| DOI: | 10.1109/tcpmt.2012.2204392 |
| Popis: | Interconnecting integrated circuits (ICs) and 3-D-ICs to the system board (printed circuit board) are currently achieved using organic or silicon-based interposers. Organic interposers face several challenges in packaging 2-D and 3-D-ICs beyond the 32-nm node, primarily due to their poor dimensional stability and coefficient of thermal expansion (CTE) mismatch to silicon. Silicon interposers made with back-end of line wafer processes can achieve the required wiring and I/O density, but their high-cost limit them to high-performance applications. Glass is proposed as a superior alternative to organic and silicon-based interposers for packaging of future ICs and 3-D-ICs with highest I/Os at lowest cost. This paper presents for the first time a novel thin and large panel glass interposer capable of scaling to 700 mm and larger panels with potential for significant cost reduction over interposers made on 200-mm or 300-mm wafers. The formation of small through vias at high speed has been the biggest technical barrier for the adoption of glass as an interposer and system substrate; and this paper describes pioneering research in via-formation in thin glass substrates, using a novel “polymer-on-glass” approach. Electrical modeling and design of through package vias (TPVs) in glass is discussed in detail, and the feasibility of 50-μm pitch TPVs in 180-μm thin glass substrates has been demonstrated. The excellent surface finish and low CTE of glass leads to increased I/O density, and increased functionality per unit area leading to system miniaturization. |
| Databáze: | OpenAIRE |
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