Automatically Retargetable Pre-Processor and Assembler Generation for ASIPs
| Autor: | Daniel Carlos Casarotto, L. Taglietti, Olinto Furtado, L.C.V. dos Santos, J.O.C. Filho |
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| Rok vydání: | 2005 |
| Předmět: |
Architecture description language
Computer science business.industry Design space exploration PowerPC Hardware description language ComputerSystemsOrganization_PROCESSORARCHITECTURES Instruction set Computer architecture Robustness (computer science) Embedded system System on a chip Code generation Hardware_CONTROLSTRUCTURESANDMICROPROGRAMMING business computer computer.programming_language |
| Zdroj: | The 3rd International IEEE-NEWCAS Conference, 2005.. |
| DOI: | 10.1109/newcas.2005.1496756 |
| Popis: | During design space exploration, alternative CPUs are evaluated for an envisaged SoC, thereby requiring fast CPU models and efficient code generation tools. Candidate CPUs may be general-purpose processors, DSPs, micro-controllers or ASIPs. The ASIP is a particularly challenging alternative: since instruction-set architecture (ISA) tailoring is allowed, an ASIP cannot rely on pre-existent code generation tools. Each target ISA requires a new tool chain. Therefore, an automatically retargetable tool chain is mandatory. This paper focuses on a couple of tools from such a chain: pre-processor and assembler. It proposes robust and efficient techniques allowing retargetability through automatic tool generation from a given target ISA, which is formally described by architecture description language (ADL) constructs. Tool robustness results from formal techniques based on context-free grammars. Tool efficiency evidence is provided by experiments targeting three CPUs: MIPS, PowerPC 405 and PIC 16F84. |
| Databáze: | OpenAIRE |
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