Vivado design interface: An export/import capability for Vivado FPGA designs
| Autor: | Thomas Townsend, Brent Nelson |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Interface (Java) Computer science business.industry CAD 02 engineering and technology Design language Data structure File format 01 natural sciences 020202 computer hardware & architecture Embedded system 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Leverage (statistics) Routing (electronic design automation) Field-programmable gate array business |
| Zdroj: | FPL |
| DOI: | 10.23919/fpl.2017.8056809 |
| Popis: | Research tools targeting commercial FPGAs have most commonly been based on the Xilinx Design Language (XDL). Vivado, however, does not support XDL, preventing similar tools from being created for next-generation devices. Instead, Vivado includes a Tcl interface that exposes Xilinx's internal design and device data structures. Considerable challenges still remain to users attempting to leverage this Tcl interface to develop external CAD tools. This paper presents the Vivado Design Interface (VDI), a set of file formats and Tcl functions that address the challenges of exporting and importing designs to and from Vivado. To demonstrate its use, VDI has been integrated with RapidSmith2, an external FPGA CAD framework. To our knowledge this work is the first successful attempt to provide an open-source tool-flow that can export designs from Vivado, manipulate them with external CAD tools, and re-import an equivalent representation back into Vivado. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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