Minority Carrier Disturb in Thyristor Memory Arrays and a Novel Cell Design for High Density DRAM

Autor:	Harry Luan, Valery Axelrad, Bruce L. Bateman, Charlie Cheng
Rok vydání:	2017
Předmět:	010302 applied physics Bit cell Engineering Fabrication business.industry Deep trench Electrical engineering Thyristor High density Carrier lifetime Cell design 01 natural sciences 0103 physical sciences Electronic engineering business Dram
Zdroj:	2017 IEEE International Memory Workshop (IMW).
DOI:	10.1109/imw.2017.7939094
Popis:	Inter-cell disturb from minority carriers is found to be one of the major problems for scaling cross-point vertical Thyristor arrays. Cell designs with minority carrier lifetime killers and deep trench isolations are either ineffective or difficult to manufacture. This paper discloses a novel MBW-VLT cell that achieves a 5F2 bit cell area, is compatible with existing DRAM fabrication tools, and devoid of any minority carrier disturbance. A well calibrated TCAD simulator is used to fully verify both DC and AC operations of cell strings.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::c082a559d402cfe143b573dc1e1c59ca https://doi.org/10.1109/imw.2017.7939094 Zobrazit plný text záznamu