A Constant Time Full Hardware Implementation of Streamlined NTRU Prime
| Autor: | Adrian Marotzke |
|---|---|
| Rok vydání: | 2021 |
| Předmět: |
Post-quantum cryptography
Key generation business.industry Computer science NTRU Hash function 020207 software engineering 02 engineering and technology VHDL 0202 electrical engineering electronic engineering information engineering NIST 020201 artificial intelligence & image processing business Field-programmable gate array computer Computer hardware Decoding methods computer.programming_language |
| Zdroj: | Smart Card Research and Advanced Applications ISBN: 9783030684860 CARDIS |
| DOI: | 10.1007/978-3-030-68487-7_1 |
| Popis: | This paper presents a constant time hardware implementation of the NIST round 2 post-quantum cryptographic algorithm Streamlined NTRU Prime. We implement the entire KEM algorithm, including all steps for key generation, encapsulation and decapsulation, and all en- and decoding. We focus on optimizing the resources used, as well as applying optimization and parallelism available due to the hardware design. We show the core en- and decapsulation requires only a fraction of the total FPGA fabric resource cost, which is dominated by that of the hash function, and the en- and decoding algorithm. For the NIST Security Level 3, our implementation uses a total of 1841 slices on a Xilinx Zynq Ultrascale+ FPGA, together with 14 BRAMs and 19 DSPs. The maximum achieved frequency is 271 MHz, at which the key generation, encapsulation and decapsulation take 4808 \(\upmu \)s, 524 \(\upmu \)s and 958 \(\upmu \)s respectively. To our knowledge, this work is the first full hardware implementation where the entire algorithm is implemented. |
| Databáze: | OpenAIRE |
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