Materials Technology Co-Optimization of Self-Aligned Gate Contact for Advanced CMOS Technology Nodes

Autor:	Keyvan Kashefizadeh, Nancy Fung, T. E. Sato, Nitin K. Ingle, W. Xu, W. Lei, Benjamin Colombeau, Anchuan Wang, Yu Lei, Ajay Bhatnagar, Ashish Pal, P. Wang, Sanjay Natarajan, D. Cui, Angada B. Sachid, Avgerinos V. Gelatos, Blessy Alexander, C. Lee, B. Brown, D. Hwang, Sean M. Seutter, K. Mikhaylichenko, T. H. Ha, M. Kawasaki, Yi Xu, Buvna Ayyagari, J. Ferrell, M. Cogorno, El Mehdi Bazizi, T. Luu
Rok vydání:	2020
Předmět:	chemistry.chemical_compound chemistry CMOS Computer science Logic gate Silicon carbide Process (computing) Electronic engineering Node (circuits) Self-aligned gate Material technology Cmos compatible
Zdroj:	2020 IEEE Symposium on VLSI Technology.
DOI:	10.1109/vlsitechnology18217.2020.9265043
Popis:	Materials technology co-optimization (MTCO) modeling is used for the first time to simulate Performance-Power-Area (PPA) benefits of self-aligned gate contact (SAGC) technology. We also demonstrate a process flow to integrate novel CMOS compatible materials and processes to enable SAGC at the 3nm node and below.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::bfd36c8e75e4bc6d493f390f472b90e4 https://doi.org/10.1109/vlsitechnology18217.2020.9265043 Zobrazit plný text záznamu