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Charge control during the source-drain implants in the CMOS process is critical to avoid damage to the thin gate dielectric. PIII has always been touted as having good charge control, since the charge deposited on the gate during the implant pulse is neutralized by the plasma electrons between pulses, thus having a ‘built in plasma flood’. However, unless the time between pulses Tbet is long, the gate can float to a positive potential in excess of 15 V. We show that Tbet can be arbitrarily reduced without inducing any gate voltage stress by applying a positive bias during this time. This requires a special ‘Charge Balance Modulator’, as well as an additional electron source. The balance of charge is measured by an in situ charge monitor, which simulates the charge on a CMOS gate. Data from this charge monitor, as well as SPIDER wafers are compared to theory. The PIII process can be considered to be a blend of ion implantation as well as plasma processing. Depending on process conditions, combinations of ion implantation, as well as plasma deposition and etch combine to yield the final dopant profile. Some of these components may be advantageous or disadvantageous, depending on the process. An important component in controlling the relative amounts of these components is the pulse width and frequency. The Charge Balance Modulator allows control of these parameters independent of charging issues. |
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