A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications

Autor:	C. W. Yeh, Yu Zhu, Asit Kumar Ray, Mark D. Drapa, Chung H. Lam, Junka Okazawa, Scott C. Lewis, Sangbum Kim, Wanki Kim, Matt BrightSky, Tu-Shun Chen, Tony Perri, Robert L. Bruce, Jack Morrish, Huai-Yu Cheng, Chia-Jung Chen, Kohji Hosokawa, Wei-Chih Chien, Thomas M. Maffitt, Richard C. Jordan, Yutaka Nakamura, Hsiang-Lan Lung, Yung-Han Ho, H. Y. Ho, Christopher P. Miller, Jerry Heath
Rok vydání:	2016
Předmět:	010302 applied physics Hardware_MEMORYSTRUCTURES business.industry Computer science Sense amplifier Registered memory Semiconductor memory 02 engineering and technology Parallel computing 01 natural sciences 020202 computer hardware & architecture Memory bank 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Interleaved memory Racetrack memory Non-volatile random-access memory Memory refresh business Computer hardware
Zdroj:	2016 IEEE 8th International Memory Workshop (IMW).
Popis:	For the first time, by using a novel multiple individual bank sensing/writing and a memory bank interleave design, we demonstrate a double date rate 2 (DDR2) DRAM like interface phase-change memory (PCM) for M-type storage class memory applications . The write and read bandwidth is equal to 533MB/s, and the random read latency is 37.5ns, while the write latency is 11.25ns supporting a random write cycle of 176.7ns. In addition, a record high switching speed of 128ns with good resistance distribution is demonstrated with a super-fast Set material.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::bf2f81e529399561583fde9227489172 https://doi.org/10.1109/imw.2016.7493563 Zobrazit plný text záznamu