Compiler assisted coalescing
| Autor: | Sooraj Puthoor, Mikko H. Lipasti |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Computer science Pipeline (computing) Translation lookaside buffer 02 engineering and technology Parallel computing computer.software_genre 01 natural sciences 020202 computer hardware & architecture Reduction (complexity) Virtual address space 0103 physical sciences Dynamic demand 0202 electrical engineering electronic engineering information engineering Overhead (computing) Compiler Hardware_CONTROLSTRUCTURESANDMICROPROGRAMMING computer Compile time |
| Zdroj: | PACT |
| Popis: | Tightly integrated CPU-GPU systems that share the same virtual address space have significantly improved the programmability of GPUs in recent years. However, to achieve this, every memory access from a GPU has to go through an address translation unit like the TLB and the huge demand on these TLBs can become a significant overhead. Previous proposals have suggested the use of an address coalescing unit that coalesces multiple accesses to the same page into a single access, significantly reducing pressure on the TLB. However, building perfect coalescing logic in real hardware is not feasible and employing a simpler hardware coalescing unit takes away many of the benefits of coalescing. In this paper, we propose compiler assisted coalescing (CAC) that significantly increases the coalescing capability of GPUs. Our CAC compiler annotates instructions that generate coalescable accesses at compile time, while simple bound checking hardware coalesces these accesses at runtime. We also introduce a translation table to the compute unit pipeline that leverages information passed from the CAC compiler to bypass the TLB, further reducing expensive TLB lookups. Evaluation of our technique on a variety of workloads shows that CAC reduces the TLB accesses by 62% with a TLB dynamic power reduction of 45%. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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