SCIPS: An emulation methodology for fault injection in processor caches
| Autor: | Nicholas Wulf, Ann Gordon-Ross, Grzegorz Cieslewski, Alan D. George |
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| Rok vydání: | 2011 |
| Předmět: |
business.industry
Cache coloring Computer science CPU cache Pipeline burst cache Hardware_PERFORMANCEANDRELIABILITY Parallel computing Cache-oblivious algorithm Cache pollution Microarchitecture Smart Cache Write-once Cache invalidation Embedded system Bus sniffing Page cache Cache business Cache algorithms |
| Zdroj: | 2011 Aerospace Conference. |
| Popis: | Due to the high level of radiation endured by space systems, fault-tolerant verification is a critical design step for these systems. 12Space-system designers use fault-injection tools to introduce system faults and observe the system's response to these faults. Since a processor's cache accounts for a large percentage of total chip area and is thus more likely to be affected by radiation, the cache represents a key system component for fault-tolerant verification. Unfortunately, processor architectures limit cache accessibility, making direct fault injection into cache blocks impossible. Therefore, cache faults can be emulated by injecting faults into data accessed by load instructions. In this paper, we introduce SPFI-TILE, a software-based fault-injection tool for many-core devices. SPFI-TILE emulates cache fault injections by randomly injecting faults into load instructions. In order to provide unbiased fault injections, we present the cache fault-injection methodology SCIPS (Smooth Cache Injection Per Skipping). Results from MATLAB simulation and integration with SPFI-TILE reveal that SCIPS successfully distributes fault-injection probabilities across load instructions, providing an unbiased evaluation and thus more accurate verification of fault tolerance in cache memories. |
| Databáze: | OpenAIRE |
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