An all digital receiver architecture for bandwidth efficient transmission at high data rates
| Autor: | M. Oerder, Heinrich Meyr, J. Stahl, Gerd Ascheid |
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| Rok vydání: | 1989 |
| Předmět: |
Very-large-scale integration
Continuous phase modulation Computer science Quantization (signal processing) Clock rate Bandwidth (signal processing) Radio receiver Digital clock manager Clock synchronization Synchronization law.invention Amplitude law Electronic engineering Electrical and Electronic Engineering Symbol rate Phase modulation Phase-shift keying Data transmission |
| Zdroj: | IEEE Transactions on Communications. 37:804-813 |
| ISSN: | 0090-6778 |
| Popis: | Using the maximum-likelihood approach, algorithms for detection and synchronization are derived that are well suited for VLSI implementation. Special emphasis is placed on an all-digital implementation where carrier and clock synchronization do not require a feedback of signals to the analog part, which simplifies the analog front-end design (mixing oscillator and A/D converter sampling clock run at fixed frequency). An important advantage of the proposed algorithms is that a high clock rate is not required; only two-four times the symbol rate is needed, depending on amplitude quantization. Implementation aspects, e.g. architecture, and quantization, are considered. A prototype is described which was implemented to prove the feasibility of the concept and to evaluate the performance under practical conditions. > |
| Databáze: | OpenAIRE |
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