Instruction cache performance of a commercial workload on the Motorola 88110 microprocessor
| Autor: | Jane Watkins, Mark Smotherman, Max J. Domeika, Darrell Suggs |
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| Rok vydání: | 1997 |
| Předmět: |
Computer Networks and Communications
CPU cache Cache coloring Computer science Pipeline burst cache Cache pollution Cache-oblivious algorithm computer.software_genre Instruction set Artificial Intelligence Write-once Cache invalidation Cache algorithms Snoopy cache Hardware_MEMORYSTRUCTURES business.industry MESI protocol MESIF protocol Smart Cache Hardware and Architecture Bus sniffing Embedded system Operating system Page cache Cache Hardware_CONTROLSTRUCTURESANDMICROPROGRAMMING business computer Least frequently used Software |
| Zdroj: | Microprocessors and Microsystems. 20:521-527 |
| ISSN: | 0141-9331 |
| DOI: | 10.1016/s0141-9331(96)01125-8 |
| Popis: | Commercial workloads, such as transaction processing, stress the memory hierarchies of current computers. TPC-B is a transaction processing benchmark that generates significant operating system and database activity, and a TPC-B instruction trace is analyzed for the Motorola 88110 microprocessor. Instruction set usage reveals one branch in every four to five instructions, and instruction cache performance indicates that this branching behavior causes a large number of words to be brought in by cache refills but never used. Code reorganization optimizations to reduce unused words and avoid cache misses are simulated and found to reduce misses in the on-chip instruction cache by almost one fifth. |
| Databáze: | OpenAIRE |
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