| Popis: |
Electrostatic discharge (ESD) problem resulting from charges on wafers is a serious concern in IC manufacturing. As is discovered in our paper, three types of defect, AA (active area) damage, IMD (Inter Metal Dielectric) crack and Via hole W corrosion that are confirmed to be induced by lithography process related ESD charging effect. We carefully studied the mechanism of these ESD charging effect by DOE splits and succeeded to dig out that these electric charge major comes from the lithography develop process. In the lithography coating and developing wafer process, the wafer will be at high spin speed at many of the steps which will easy help to store the electric charge on the wafer. In our study, the rinse step in developing process is the most key factor to store the electric charge on wafer. In generally, the higher rinse speed, the higher positive electric charge. Furthermore, we also discovered that the different step in develop rinse process have different impact on charge level, in which the acceleration and deceleration step has the highest charge voltage. As to minimize and eliminate the ESD damage in lithography process, we finally carry out the simplified recipe optimization solution which only need optimize for the develop rinse speed with different in-coming surface charge level and process application, so that can be easy implemented in the worldwide fabs. |
