| Autor: |
Gil Heyun Choi, Myoung Bum Lee, Sang Bom Kang, Kwang Jin Moon, Young Wook Park, Hee Sook Park, Joo Tae Moon |
| Rok vydání: |
2002 |
| Předmět: |
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| Zdroj: |
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517). |
| DOI: |
10.1109/vtsa.2001.934491 |
| Popis: |
The implementation of W bit-line enabled the integration of n+ and p+ common contact process at bit-line level. Despite the advantages of the common contact process such as chip-area reduction and elimination of the burden associated with MC dry etch, the immediate implementation of the common contact is difficult due to large increase of p+ contact resistance with high thermal budget capacitor process. The results of the present investigation indicate that the thickness of TiSi/sub 2/ layer must be minimized in order to prevent the out-diffusion of boron into silicide layer. However, simply reducing the thickness of TiSi/sub 2/ presents another problem since it leads to a discontinuous layer of TiSi/sub 2/. Heavily increasing the dosage of p+ plug implantation, which is another way of preventing the depletion of boron dopants, resulted in degradation of p+ contact resistance. Therefore, the dopant out-diffusion alone cannot explain the degradation of p+ contact resistance. In order to minimized the thickness of TiSi/sub 2/, enhanced nitridation after deposition of PECVD-Ti was tested and resulted in effective reduction of the p+ contact resistance by 25%. The TEM and SIMS analysis showed that the additional growth of TiSi/sub 2/ during high thermal budget post annealing was suppressed by the enhanced nitridation. The mechanism responsible for reducing the p+ contact resistance by the enhanced nitridation is attributed to the prevention of the dopant depletion at the interface between TiSi/sub 2/ and Si due to the suppressed formation of additional TiSi/sub 2/. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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