Process and design optimization of a protection scheme based on NMOSFETs with ESD implant in 65nm and 45nm CMOS technologies

Autor:	Kiran V. Chatty, David Alvarez, C. Russ, Robert J. Gauthier, B.J. Kwon, Michel J. Abou-Khalil
Rok vydání:	2007
Předmět:	Reduction (complexity) Electrostatic discharge Materials science CMOS business.industry MOSFET Electrical engineering Process (computing) Implant business Voltage
Zdroj:	2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).
Popis:	Process and design optimization of NMOSFETs with ESD implant is presented. A 2 V reduction in trigger voltage, a 30% higher failure current, 50% reduction in on-resistance is achieved with a 13X increase in leakage current for a 2.5 V NMOSFET. Self-protected NMOSFETs with ESD implant enables 40% or larger decrease in NMOSFET area for a non-mixed voltage and mixed voltage I/O.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::bde2b4472ac07669dc1b4e86edeb04aa https://doi.org/10.1109/eosesd.2007.4401777 Zobrazit plný text záznamu