| Autor: |
Jinsun Kim, Seung Yoon Lee, Peter Nikolsky, Wim Tjibbo Tel, Jin-Ho Lee, Koen Thuijs, Hyun-Woo Yu, Yuxiang Yin, Sunyoung Yea, Kim Sang-Uk, Denis Ovchinnikov, Harm Dillen, Jeongjin Lee, Young-Hoon Song, Jae-Seung Jeong, Yun-A Sung, Kaustubh Padhye, James Lee, Antonio Corradi, Joon-Soo Park, Isabel de la Fuente Valentin, Miao Wang, Marc Kea, Daan Slotboom, Vadim Timoshkov, Daniel Park, Jin-Woo Lee, Rhys Su, Chan Hwang, Sun Wook Jung, Oh-Sung Kwon |
| Rok vydání: |
2020 |
| Předmět: |
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| Zdroj: |
Metrology, Inspection, and Process Control for Microlithography XXXIV. |
| Popis: |
In leading edge patterning processes, overlay is now entangled with CD including OPC residuals and stochastics. This combined effect is a serious challenge for continued shrink and can be characterized with an Edge Placement Error (EPE) budget containing multi-domain components: global and local CD, local placement errors, overlay errors, etch biases and OPC. EPE defines process capability and ultimately relates to device yield. Understanding the EPE budget leads to efficient ways to monitor process capability and optimize it using EPE based process control applications. We examine a critical EPE use case on a leading edge DRAM node. We start by constructing and verifying the EPE Budget via densely sampled on-product in-device local, global CD and Overlay metrology after the etch process step. EPE budget contributors are ranked according to their impact to overall EPE performance and later with simulated EPE performance improvements per component. A cost/benefit analysis is shown to help choose the most HVM-friendly solutions. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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