An Experimental Result on the Effect of Bypass Capacitance in Load Board for Semiconductor's Speed Testing
| Autor: | Johan, M. Phoon, S.M. Low, A. Suffian |
|---|---|
| Rok vydání: | 2008 |
| Předmět: |
Engineering
business.industry Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Integrated circuit Decoupling capacitor computer.software_genre Capacitance law.invention Capacitor Load testing Printed circuit board law Hardware_INTEGRATEDCIRCUITS Device under test Routing (electronic design automation) business computer |
| Zdroj: | 2008 10th Electronics Packaging Technology Conference. |
| DOI: | 10.1109/eptc.2008.4763592 |
| Popis: | Load board is a multi-layered printed circuit boars (PCB) commonly used as an interface device between the test equipment and the device under test (DUT) in semiconductor IC testing. Since the PCB contains capacitors and conductive traces for routing the DUT to the tester, the performance of the load board becomes critical in the realm of high speed semiconductor testing. This paper showed the effect of different values of bypass capacitors used in the load board on testing semiconductor's high speed function. The testing was based on one of the test pattern of the Communication Processor Module of the IC. Trace impedance of the load boards was verified to be designed and fabricated according to impedance control and design requirement using Time domain Reflectometry. Shmoo results clearly showed significant differences for the same DUT when the two load boards were used. This result indicated that the values of the bypass capacitor affected the outcome of the semiconductor's speed sorting. If one is not careful with the proper choice of the bypass capacitance, the production could face the risk of binning good units of the device into wrong bin and eventually be scrapped although they actually can perform well at the required speed. This implies production loss. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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