A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Autor:	Jihi-Yu Lin, Wei-Chiang Shih, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Chien-Yu Lu, Meng-Hsueh Wang, Yuh-Jiun Lin, Kuen-Di Lee
Rok vydání:	2012
Předmět:	Soft error CMOS Subthreshold conduction Computer science Electronic engineering Static random-access memory Electrical and Electronic Engineering Standby power Low voltage Word (computer architecture) Threshold voltage
Zdroj:	IEEE Journal of Solid-State Circuits. 47:1469-1482
ISSN:	1558-173X 0018-9200
DOI:	10.1109/jssc.2012.2187474
Popis:	This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with VDD down to 0.35 V ( 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 μW power. Data is held down to 0.275 V with 2.29 μW Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for VDD around/above 1.0 V.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::bd783eb5c6527b83a5514c06b956efde https://doi.org/10.1109/jssc.2012.2187474 Zobrazit plný text záznamu