A 53–61GHz Low-Power PLL With Harmonic Positive Feedback VCO in 65nm CMOS
| Autor: | Omeed Momeni, Rouzbeh Kananizadeh, Razieh Abedi, Amir Esmaili, Payam Heydari |
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| Rok vydání: | 2018 |
| Předmět: |
Computer science
020208 electrical & electronic engineering Transistor dBc 020206 networking & telecommunications 02 engineering and technology law.invention Harmonic analysis Frequency divider Phase-locked loop Voltage-controlled oscillator CMOS law Phase noise 0202 electrical engineering electronic engineering information engineering Harmonic Electronic engineering Positive feedback Voltage |
| Zdroj: | ISCAS |
| Popis: | A 53–61GHz low-power charge-pump PLL is presented. This integer-N type-II PLL employs a class-D V-band VCO and a divide-by-1024 chain. The first divider in the chain is an inductor-less divide-by-4 injection-locked frequency divider (ILFD). The proposed PLL is fabricated in a standard 65nm CMOS process. The VCO employs a harmonic positive feedback technique to boost the fundamental signal swing, which leads to better phase noise performance at low supply voltage and DC power consumption compared to prior work. The VCO consumes the minimum power of 10.6mW from 0.8V supply. The PLL achieves a wide tuning range of 13% from 53.35- to 60.83-GHz and a phase noise of −88 dBc/Hz at 1MHz offset, while consuming a minimum DC power of 48mW. This PLL can be used as part of the LO generation network for millimeter-wave phased-array transceivers. |
| Databáze: | OpenAIRE |
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